Individual Flow Complete

The digital design flow is complete. RJ has sent me the synthesis libraries that he had converted. I have tested them using Leonardo Spectrum for a simple counter. I then simulated the synthesised counter at behavioural level using ModelSim. After that I simulated it at transistor level using Eldo. Both work and produce similar results.

Note: VHDL vectors should be numbered in ascending order, i.e. 0 to 7 instead of 7 to 0. This is because EZWave doesn’t seem to allow me to reorder the individual bits of a bus. As a result the counter counts 0, 128, 64 …. instead of  0, 1, 2 ….

As for the analogue flow, I have managed to design, layout and simulate a simple custom NOR2 gate. So, that is working as well.

I should think that we should work out the details of the final design, so that I can start writing up the individual flows while I work out the integrated flow.

Published by

Shawn Tan

Chip Doctor, Chartered/Professional Engineer, Entrepreneur, Law Graduate.

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