The digital tool flow should work without any problems.
I’d suggest using Emacs to write the VHDL code as it has a built-in language mode that is extremely helpful by ensuring that code is written in correct syntax. The built-in mode also checks the syntax using Modelsim. Modelsim will also simulate the digital code without any problems.
Leonardo can be run under WINE in full GUI mode without problems. It can synthesise the digital design using standard cells. RJ says that he will convert the libraries for us as soon as he can. So, we should be able to synthesis VHDL code to the AMS 0.35 standard cells. It is important to output the final synthesised netlist in Verilog. This will allow it to be imported into ICStudio for back-end work.
The synthesised netlist should simulate under Modelsim as well. I have already imported the AMS 0.35u VITAL, Vtables, Vcomponent VHDL libraries into Modelsim’s own internal library.