I’ve had some success with the analogue toolchain.
The previous problem with the ELDO simulation had been solved. The problem wasn’t with the model netlisting but the library inclusion. When the correct library is included, the custom models are found. I had assumed that the correct library would be included by default, which wasn’t the case. The library has to be explicitly selected using the built in design kit menu command. This allows the selection of various values: worst, typical, best. So, ELDO simulation at the transistor level works.
The next issue I faced was with SDL layout. The default transistors generated by Mentor will not pass LVS as they do not include substrate taps. Therefore, the generated devices need to be changed from “cgc” to “cgct” in order to include the taps. However, where “t” appears depends on the design. So, the students will need to experiment with the positioning of the substrate tap. Routing should be done manually using IRoute instead of auto-routing with ARoute. Otherwise, it may not meet DRC checks.
I have also successfully used Calibre to perform the LVS checks. I haven’t had time to do DRC/PEX but the AMS website does have instructions for them. Performing all the necessary modifications in order to meet DRC may be troublesome. I’ll need to keep track of all the different design rules. I’ve downloaded the document and I may print it out for reference.
Once all the issues have been resolved, I will try to do a mixed layout using ICStudio. The AMS website doesn’t have instructions for mixed designs. It does have instructions for standard cell layout. So, it might be necessary to do the analogue and digital layouts separately before integrating them only at the top-level of the chip.