AMS 0.35u HitKit 3.70 Update

Hierarchical Layout
ECB has successfully installed the latest HitKit and I have taken it for a test. It does not work with the latest Mentor ICFlow 2007. However, it is able to work with the slightly older 2006 version. It integrates nicely with ICStudio, allowing a more intuitive work flow than the older 3.51 HitKit. However, as the present installation of ICFlow 2006 doesn’t work with the installed simulator, I am unable to test out either device level (analogue) simulation, nor cell level (digital) simulation. I could also not test Calibre as the installed version is too new to work with the HitKit.

We’ve notified JPN that we’d like to install the supported versions of Mentor tools from EUROPRACTICE. The tools versions are slightly older than the ones we have installed. Hopefully, they’ll work nicely together.

While waiting for ECB to install the latest HitKit, I wrote a bunch of Verilog netlists for the standard devices as were part of the previous VLSI project, such as the counter, shift register and gates. A full parts list available in the standard cell library is available here:

http://asic.austriamicrosystems.com/databooks/index_c35.html

I then followed the instructions provided by AMS to bring a ring-oscillator design into final layout. The screenshot is of the tiny ring oscillator, surrounded by 2 output buffers, 1 input buffer, VCC, GND. It also has corner cells and filler cells. The instructions are given here:

http://asic.austriamicrosystems.com/hitkit/hk370/icstation/index.html

I was successful in:

  1. Importing a Verilog netlist into a schematic/symbol.
  2. Creating all the viewpoints (device, cell, apar) from the generated schematic.
  3. Using the generated schematics inside a top level wrapper with I/O pads.
  4. Doing a hierarchical layout of this design, with I/O pads, corner cells and filler cells from the HitKit.

I can assume that simulation should work, once the tools are installed properly. I have previously been able to simulate the design with the 2007 version of ICFlow. I will also assume that Calibre should work, as the instructions from AMS clearly state the necessary steps to perform verification.

Therefore, I can quite confidently say that we can build a design project out of this toolchain + design kit, once the other tools are correctly installed.

Tasks that need to be done:

  1. Choose a suitable design that can be built easily, using limited standard cell parts. Essentially, there are flipflops (D, T, JK), logic gates (XOR, XNOR, NOR, NAND, INV), adders (1-bit HALF, FULL), muxes, latches. The full parts list also provides speed, power and area estimates, which may be useful for deciding which parts to use.
  2. Adapt the instructions given by AMS into a manual. Although the steps are generally quite clear, the selections only make sense to someone who has done it before. Some information may need to be provided to help them understand how to do the top level integration of the design.

I would propose that the project be done in the following manner:

  • Week #1: Bring them through a quick design of a single ring oscillator, using standard cells, from HDL through to final layout. The idea is to familiarise themselves with the flow and toolchain. It took me about 2 hours to go through the motions. So, 8 hours should be sufficient for design import (they can look at the code/schematic), simulation (cell/device), layout.
  • Week #2: Get them to do their design in structural HDL, simulation and verification. All this can be accomplished from within ICStudio although other tools may be better. Emacs has a built in VHDL mode and a Verilog mode can be downloaded from the net.
  • Week #3: Design a custom NAND/NOR gate from transistor, simulation and verification. Integrate this gate into a new ring-oscillator.
  • Week #4: Bring their final design through to layout, LVS, DRC, XRC.
  • Week #4: (Optional) Verification of post layout design, using back annotation + possibly SDL.

Published by

Shawn Tan

Chip Doctor, Chartered Engineer, Entrepreneur, Law Graduate.

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