We have started making some progress with the installation and setup of the Mentor software. Due to the difference in the versions for the AMI05 design kit and the latest Mentor version, the instructions for using the DK are essentially non-applicable. So, I am trying to figure out how to work the DK from within the latest Mentor setup.
The MGC_DESIGN_KIT can be manually specified from within ICSTUDIO. This means that the old mgc_location_map file is not really relevant anymore. The /parts folder contains circuit symbols ONLY.
Schematic capture within DA_IC works as before. When the correct AMI05 library is added, all the standard cells can be inserted into the schematic. I tested it by building a RINGOSC schematic using 17 NAND gates.
Schematic Driven Layout
SDL works only if the layout cells are specified correctly. At the moment, I cannot figure out how to specify this directly. Therefore, the work-around that I’m using is copying all the layouts for each standard cell into the /parts folder. So, it now contains symbols AND layouts. If I can figure out how to tell ICSTATION to look for the layouts in a different folder, we can leave the DK as it is.
Auto Place & Route
APR doesn’t work as the userware script calls a programme (lconvt) that doesn’t seem to exist. So, the next best thing to do is to use SDL and that works. It produces similar results, as can be seen in the figure. I will not encourage using it for large designs though. Therefore, the final design that we use may need to be partitioned properly.
The generated layout FAILS LVS. I will need to investigate why the nand instance names changed from ND2 to X_ND2, which is the reason why LVS fails. I cannot seem to invoke Calibre for DRC/PEX checking from anywhere. I’m guessing that there must be some missing environment variable somewhere.
VHDL/Verilog Design Entry
I’m able to edit Verilog files directly from ICStudio. It also invokes Modelsim to check the code for errors. I’m only going to test it with Verilog but I assume that VHDL works the same way. I will need to get Leonardo Spectrum installed before I can test SYNTHESIS. It has still not been installed at the moment because SJM has discovered that it doesn’t run on Linux. We will try to run it on Windows instead. I can see menus in ICSTUDIO that allow Verilog netlists to be directly imported. I’m assuming that it will be able to generate a schematic from the Verilog netlist, in order for backend work to be done.
I can simulate RTL code directly within ModelSim. It seems that DA_IC is also capable of invoking modelsim internally and viewing the output data in EZwave. This will be preferable for simulating post synthesis designs. I will have to investigate how to set this up correctly. At the moment, it doesn’t quite work as it is unable to find the references used.
There is a /quickhdl directory that seems to contain the necessary simulation data for the standard cells. However, I have yet to figure out how to tell Modelsim to use this. There should be some command line parameter or something that I can pass it to get it to work.