I’ve just spoken to SJM, this afternoon, about the status of the RedHat Servers. It is something that they’re doing very soon and he told me that they should have it all set up in the next couple of days. Hopefully, I’ll be able to start looking at the design kit compatibilities asap.
He mentioned that he might want to try running it on the SuSE system to see if it works on it. If it does (there isn’t a real reason why it should not), then we may just run them off SuSE instead.
I’ve discovered something interesting called the ASIC Design Kit (ADK), which is a generic design kit provided by mentor under their Higher Education Programme. However, I’m not sure if we have access to the ADK as it is not listed directly on either the EUROPRACTICE site nor the RAL site.
From the ADK documentation, the target technologies are AMI 0.5m and 1.2m and TSMC 0.35m, 0.25m and 0.18m. This is good as we have direct access to the AMIS 0.5um backend design kit and we only need one foundry process for teaching purposes. From the ADK documentation, the kit provides:
- Support for schematic, HDL or mixed schematic/HDL based designs
- Synthesis support for Leonardo Spectrum
- Pre-layout timing simulations with QuickSim and ModelSim (VHDL or Verilog)
- Scan insertion support for DFTAdvisor
- Automatic test pattern generation support for FastScan or FlexTest
- Static timing analysis models for SST Velocity
- Automatic place and route of designs using IC Station
- Post-layout timing simulations with QuickSim, ModelSim (VHDL/Verilog), Mach TA, or Eldo
- Support for Design Architect-IC
Therefore, it provides us with everything we need. Hopefully, we can get access to the ADK directly. This will solve our design kit problems forever as it is supported directly by Mentor. Otherwise, I will have to fall-back onto a backup plan for using the AMIS 0.5um design kit, which seems to be the most promising as it has support from front-to-back for the design flow.